74ALVC16836A
20-bit registered driver with inverted register enable; 3-state
Rev. 2 — 12 September 2018 Product data sheet
1. General description
The 74ALVC16836A is a 20-bit universal bus driver. Data flow is controlled by active low output
enable (OE), active low latch enable (LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or
HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-
flop.
When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking
capability of the driver.
2. Features and benefits
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low-power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple V
CC
and GND pins for minimum noise and ground bounce
• Output drive capability 50 Ω transmission lines at 85°C
• Input diodes to accommodate strong drivers
• Complies with JEDEC standard no. 8-1A
• Complies with JEDEC standards:
• JESD8-5 (2.3 V to 2.7 V)
• JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
• CDM JESD22-C101E exceeds 1000 V
3. Ordering information
Table 1. Ordering information
PackageType number
Temperature range Name Description Version
74ALVC16836ADGG −40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
SOT364-1
Nexperia
74ALVC16836A
20-bit registered driver with inverted register enable; 3-state
4. Functional diagram
aaa-026917
D
OE
CP
LE
A1
Y1LE
CP
Fig. 1. Logic diagram
aaa-029024
55
54
52
51
49
48
47
45
1
EN1OE
A1
A2
A3
A4
A5
A6
A7
A8
3D 11
3
2
5
6
8
9
10
12
Y2
Y3
Y4
Y5
Y6
Y7
Y8
44
A9
13
Y9
43
A10
14
Y10
42
A11
15
Y11
41
A12
16
Y12
40
A13
17
Y13
38
A14
19
Y14
37
A15
20
Y15
36
A16
21
Y16
34
A17
23
Y17
31
A19
26
Y19
30
A20
27
Y20
33
A18
24
Y18
29
C3
G2
LE
Y1
56
2C3CP
Fig. 2. Logic symbol (IEEE/IEC)
002aac725
A1
V
CC
Fig. 3. Typical input (data or control)
74ALVC16836A All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 2 — 12 September 2018 2 / 14