AN-436-4.0

AN 436: Using DDR3 SDRAM in Stratix III

and Stratix IV Devices

Introduction

DDR3 SDRAM is the latest generation of DDR SDRAM technology, with improvements that

include lower power consumption, higher data bandwidth, enhanced signal quality with

multiple on-die termination (ODT) selection and output driver impedance control.

DDR3 SDRAM brings higher memory performance to a broad range of applications, such as

PCs, embedded processor systems, image processing, storage, communications, and

networking.

Although DDR2 SDRAM is currently the more popular SDRAM, to save system power and

increase system performance you should consider using DDR3 SDRAM. DDR3 SDRAM

offers lower power by using 1.5 V for the supply and I/O voltage compared to the 1.8-V

supply and I/O voltage used by DDR2 SDRAM. DDR3 SDRAM also has better maximum

throughput compared to DDR2 SDRAM by increasing the data rate per pin and the number

of banks (8 banks are standard).

1 The Altera

ALTMEMPHY megafunction and DDR3 SDRAM high-performance

controller only support local interfaces running at half the rate of the memory

interface.

Altera Stratix

III and Stratix IV devices support DDR3 SDRAM interfaces with dedicated

DQS, write-, and read-leveling circuitry.

Table 1 displays the maximum clock frequency for DDR3 SDRAM in Stratix III devices.

Table 1. DDR3 SDRAM Maximum Clock Frequency Supported in Stratix III Devices (Note 1), (2)

Speed Grade f

MAX

(MHz)

–2 533 (3)

–3 and I3 400

–4, 4L, and I4L at 1.1 V 333 (4), (5)

–4, 4L, and I4L at 0.9 V Not supported

Notes to Table 1:

(1) Numbers are preliminary until characterization is final. The supported operating frequencies are memory interface maximums for the device

family. Your design's actual achievable performance is based on design and system specific factors and static timing analysis of the completed

design.

(2) Applies to modules and components using fly-by termination with leveling scheme.

(3) Timing can close at the target speed in the Quartus II software version 8.0. In Quartus II software version 8.1, you can use these designs for

prototyping, but you should not go to production until Altera releases final DDR3 models in Quartus II software version 9.0..

(4) Performance is based on 1.1-V core voltage. At 1.1-V core voltage, the –4L speed grade devices have the same performance as the –4 speed

grade devices.

(5) The Quartus II software version 8.1 does not support DDR3 SDRAM below 360 MHz. The DLL mode is not supported below 360 MHz. The

Quartus II software incorrectly shows that the design meets I/O timing.

Page 2 Background

AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 Altera Corporation

f For more information on DDR3 SDRAM Maximum Clock Frequency Supported in

Stratix IV Devices, refer to the External Memory Interfaces chapter in the Stratix IV

Device Handbook.

This application note describes the FPGA design flow to implement external memory

interfaces using Stratix III and Stratix IV devices, and provides design guidelines.

DDR3 SDRAMs are available as components and modules, such as DIMMs,

SODIMMs, and RDIMMs. This application note describes implementing DDR3

SDRAM with Stratix III, Stratix IV, HardCopy

III, or HardCopy IV devices, including

information on electrical and timing analysis, and the generation of a complete

board-level system that you may use to demonstrate and validate the interface.

Stratix III and Stratix IV devices feature a similar input/output element (IOE)

structure, so they effectively have the same external memory interface capabilities.

HardCopy III and HardCopy IV devices may also be considered to have identical

capabilities to their companion devices.

1 Throughout this document, statements made for Stratix III devices apply equally for

Stratix IV, HardCopy III, and HardCopy IV devices, unless otherwise mentioned.

Background

This section gives background information on the following topics:

■ DDR3 SDRAM Overview

■ IOE Dedicated DDR3 SDRAM Features

■ DDR3 SDRAM Interface Termination and Topology

■ ALTMEMPHY Megafunction Overview

DDR3 SDRAM Overview

DDR3 SDRAM is internally configured as an eight-bank DRAM. DDR3 SDRAM uses

an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch

architecture is combined with an interface that transfers two data words per clock

cycle at the I/O pins. A single read or write operation for DDR3 SDRAM consists of a

single 8n-bit wide, four-clock data transfer at the internal DRAM core and two

corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read

and write operations to the DDR3 SDRAM are burst oriented. Operation begins with

the registration of an active command, which is then followed by a read or write

command. The address bits registered coincident with the active command select the

bank and row to be activated (BA0 to BA2 select the bank; A0 to A15 select the row).

The address bits registered coincident with the read or write command select the

starting column location for the burst operation, determine if the auto precharge

command is to be issued (via A10), and select burst chop (BC) of 4 or burst length (BL)

of 8 mode at runtime (via A12), if enabled in the mode register. Before normal

operation, the DDR3 SDRAM must be powered up and initialized in a predefined

manner.