Page 2
Zynq®-7000 AP SoC Family
Cost-Optimized Devices Mid-Range Devices
Device Name
Z-7007S Z-7012S Z-7014S Z-7010 Z-7015 Z-7020 Z-7030 Z-7035 Z-7045 Z-7100
Part Number
XC7Z007S
XC7Z012S
XC7Z014S
XC7Z010
XC7Z015
XC7Z020
XC7Z030 XC7Z035 XC7Z045 XC7Z100
Processing
System (PS)
Processor Core
Single-Core
ARM® Cortex™-A9 MPCore™
Up to 766MHz
Dual-Core
ARM Cortex-A9 MPCore
Up to 866MHz
Dual-Core
ARM Cortex-A9 MPCore
Up to 1GHz
(1)
Processor Extensions
NEON™ SIMD Engine and Single/Double Precision Floating Point Unit per processor
L1 Cache
32KB Instruction, 32KB Data per processor
L2 Cache
512KB
On-
Chip Memory
256KB
External Memory Support
(2
)
DDR3, DDR3L, DDR2, LPDDR2
External Static Memory Support
(2
)
2x Quad-SPI, NAND, NOR
DMA Channels
8 (4 dedicated to PL)
Peripherals
2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
Peripherals w/ built-in DMA
(2)
2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO
Security
(3)
RSA Authentication of First Stage Boot Loader,
AES and SHA 256b Decryption and Authentication for Secure Boot
Processing System to
Programmable Logic Interface Ports
(Primary Interfaces & Interrupts Only)
2x AXI 32b Master, 2x AXI 32b Slave
4x AXI 64b/32b Memory
AXI 64b ACP
16 Interrupts
Programmable
Logic (PL)
7 Series PL
Equivalent
Artix®-7 Artix-7 Artix-7 Artix-7 Artix-7 Artix-7 Kintex®-7 Kintex-7 Kintex-7 Kintex-7
Logic
Cells
23K 55K 65K 28K 74K 85K 125K 275K 350K 444K
Look-
Up Tables (LUTs)
14,400 34,400 40,600 17,600 46,200 53,200 78,600 171,900 218,600 277,400
Flip-
Flops
28,800 68,800 81,200 35,200 92,400 106,400 157,200 343,800 437,200 554,800
Total Block
RAM
(# 36Kb
Blocks)
1.8Mb
(50)
2.5Mb
(72)
3.8Mb
(107)
2.1Mb
(60)
3.3Mb
(95)
4.9Mb
(140)
9.3Mb
(265)
17.6Mb
(500)
19.2Mb
(545)
26.5Mb
(755)
DSP
Slices
66 120 170 80 160 220 400 900 900 2,020
PCI Express®
— Gen2 x4 — — Gen2 x4 — Gen2 x4 Gen2 x8 Gen2 x8 Gen2 x8
Analog Mixed Signal (AMS) / XADC
(2)
2x 12 bit, MSPS ADCs with up to 17 Differential Inputs
Security
(3)
AES & SHA 256b Decryption & Authentication for Secure Programmable Logic Config
Speed Grades
Commercial
-1 -1 -1
-1
Extended
-2 -2,-3
-2,-3
-2
Industrial
-1, -2
-1, -2, -1L -1, -2, -2L -1, -2, -2L
Notes:
1. 1 GHz processor frequency is available only for -3 speed grades for devices in flip-chip packages. Please see the data sheet for more details.
2. Z-7007S and Z-7010 in CLG225 have restrictions on PS peripherals, memory interfaces, and I/Os. Please refer to the Technical Reference Manual for more details.
3. Security block is shared by the Processing System and the Programmable Logic.
Page 3
Zynq®-7000 All Programmable SoC Family
HR I/O, HP I/O, PS I/O, and Transceivers (GTP or GTX)
Cost-Optimized Devices Mid-Range Devices
Device Name
Z-7007S Z-7012S Z-7014S Z-7010 Z-7015 Z-7020 Z-7030 Z-7035 Z-7045 Z-7100
Package
Footprint
Dimensions
(mm)
(1)
Ball Pitch
(mm)
HR I/O, HP I/O
PS I/O
(2)
, GTP Transceivers
HR I/O, HP I/O
PS I/O
(2)
, GTX Transceivers
CLG225
13x13 0.8
54, 0
84
(3)
, 0
54, 0
84
(3)
, 0
CLG400
17x17 0.8
100, 0
128, 0
125, 0
128, 0
100, 0
128, 0
125, 0
128, 0
CLG484
19x19 0.8
200, 0
128, 0
200, 0
128, 0
CLG485
(4)
19x19 0.8
150, 0
128, 4
150, 0
128, 4
SBG485
(4)
19x19 0.8
50, 100
128, 4
FBG484
23x23 1.0
100, 63
128, 4
FBG676
(1)
27x27 1.0
100, 150
128, 4
100, 150
128, 8
100, 150
128, 8
FFG676
(1)
27x27 1.0
100, 150
128, 4
100, 150
128, 8
100, 150
128, 8
FFG900
31x31 1.0
212, 150
128, 16
212, 150
128, 16
212, 150
128, 16
FFG1156
35x35 1.0
250, 150
128, 16
Notes:
1.
Devices in the same package are footprint compatible. FBG676 and FFG676 are also footprint compatible.
2.
PS I/O count does not include dedicated DDR calibration pins.
3.
PS DDR and PS MIO pin count is limited by package size. See DS190, Zynq-7000 All Programmable SoC Overview for details.
4.
CLG485 and SBG485 are pin-to-pin compatible. See product data sheets and user guides for more details.
See DS190, Zynq-7000 All Programmable SoC Overview for package details.