Revision B, 09.09.02 Page1of12
ANALOG IP BLOCK
CDAC12 - CMOS 12-Bit D/A CONVERTE R
DATA SHEET
FEATURES
! Small Area: 2mm
2
! Size: x = 995µm y = 2021µm
! Supply Voltage: 3.0 to 3.6V
! Junction Temp. Range: −40 to +125°C
! Resolution: 12-Bit
! Maximum Update Rate: 200MS/s
! Diff. Current Outputs: 10 to 20mA
! Power of 150mW @ 3.3V Supply Voltage and 10mA
output current
DESCRIPTION
The CDAC12 is a 12-bit high-resolution high-speed CMOS digital-to-
analog converter (DAC).
The CDAC12 uses a segmented current steering architecture
combined with a simple and fast decoding logic to achieve a very high
update rate, 12-bit of intrinsic static accuracy, and good dynamic
characteristics.
The CDAC12 is a differential current output DAC with a typical full-
scale current of 10mA or 20mA. The output currents can be used to
directly drive two external resistors to obtain two complementary
output voltages, or they can be used to drive an external transformer
(or amplifier) to obtain a single-ended output voltage.
V
DDS
V
DDD
V
SSA
V
SSS
INPUT REGENERATION
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
ROW DECODER
COLUMN DECODER
6 MSB SWITCHES
CURRENT
SOURCE ARRAY
4LSB
SWITCHES
FOUR
BINARY
CURRENT
SOURCES
BIAS
GENERATION
CLK
IOUTN IOUTP IBIAS
B
11
B
10
4ISB
SWITCHES
FOUR
EQUAL
CURRENT
SOURCES
6
2
4
V
DDA
V
SSD
PROCESS
C35B3 (0.35um)
Datasheet : CDAC12 – C35
Revision B, 09.09.02 Page2of12
TECHNICAL DATA FOR OUTPUT CURRENT=10mA
(Tjunction=–40 to 125°C, VDDA=VDDD=+3.0V to +3.6V, fclk=200MHz, R
L
=50Ω, unless otherwise specified)
DC SPECIFICATIONS
Symbol Parameter Conditions Min Typ Max Units
Resolution 12 bit
DNL Differential Linearity Error –1
±0.7
+1 LSB
INL Integral Linearity Error –2
±0.7
+2 LSB
REFERENCE INPUT
Symbol Parameter Conditions Min Typ Max Units
IBIAS Reference Current I
FS
/16 I
FS
/16 I
FS
/16 mA
ANALOG OUTPUT
Symbol Parameter Conditions Min Typ Max Units
OFFSETB Offset Error –5 0 +5 % FS
FSERR Full-Scale Error –5 1 +5 % FS
I
FS
Full-Scale Output Current 8 10 12 mA
V
FS
Output Compliance Range 0.5 0.6 V
R
out
Output Resistance 100
kΩ
C
out
Output Capacitance 12 pF
f
outmax
Max. Output Signal Frequency 30 MHz
AC ACCURACY (fclk=200MHz)
Symbol Parameter Conditions Min Typ Max Units
THD Total Harmonic Distortion f
out
=1MHz –80 dBc
THD Total Harmonic Distortion f
out
=10MHz –54 dBc
THD Total Harmonic Distortion f
out
=30MHz –42 dBc
SFDR Spurious Free Dynamic Range f
out
=1MHz 71 dBc
SFDR Spurious Free Dynamic Range f
out
=10MHz 59 dBc
SFDR Spurious Free Dynamic Range f
out
=30MHz 42 dBc
AC ACCURACY (fclk=100MHz)
Symbol Parameter Conditions Min Typ Max Units
THD Total Harmonic Distortion f
out
=0.5MHz –81 dBc
THD Total Harmonic Distortion f
out
=5MHz –63 dBc
THD Total Harmonic Distortion f
out
=15MHz –54 dBc
SFDR Spurious Free Dynamic Range f
out
=0.5MHz 71 dBc
SFDR Spurious Free Dynamic Range f
out
=5MHz 70 dBc
SFDR Spurious Free Dynamic Range f
out
=15MHz 55 dBc
TT-IMD Two-Tone Third Order Intermodulation
Distortion
f
out1
=10MHz
1)
f
out2
=11MHz
–60 dBc
TT-SFDR Two-Tone
Spurious Free Dynamic Range
f
out1
=10MHz
1)
f
out2
=11MHz
60 dBc
1)
Both signals, f
out1
and f
out2
, have an amplitude of –6dB full scale.