EN256 (v1.5) December 16, 2016 www.xilinx.com
Errata Notification 1
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Introduction
Thank you for designing with the Xilinx Defense-Grade Zynq®-7000Q family of devices. Although Xilinx has made every
effort to ensure the highest possible quality, the devices listed in Table 1 are subject to the limitations described in the
following errata.
Devices
These errata apply to the devices shown in Table 1.
Processor System (PS) Errata Details
This section provides a detailed description of each processor system issue known at the release time of this document,
including applicable errata from third-party IP, which has been modified to reflect implementation in the devices listed in
Table 1. Additional information for each issue is available in the associated answer record. For a disposition of each ARM
Cortex-A9 errata, see Answer Record 55518
.
APU
Under Very Rare Timing Circumstances, Transition Into Streaming Mode Might Create A
Data Corruption
Answer Record 65545
Under very rare timing circumstances, a data corruption might occur on a dirty cache line that is evicted from the L1 Data
Cache due to another cache line being entirely written.
The erratum requires the following conditions:
• The CPU contains a dirty line in its data cache.
• The CPU performs at least four full cache line writes, one of which is causing the eviction of the dirty line.
• Another CPU, or the ACP, is performing a read or write operation on the dirty line.
This is a third-party errata (ARM, Inc. 845369); this issue will not be fixed.
Defense-Grade Zynq-7000Q AP SoCs:
Production Errata
EN256 (v1.5) December 16, 2016 Errata Notification
Table 1: Devices Affected by These Errata
Product Family Device
JTAG ID
(Revision Code)
Package Speed Grade
Junction
Temperature Range
Zynq-7000Q XQ7Z020 2 or later All All All
XQ7Z030 1 or later
XQ7Z045 2 or later
XQ7Z100 0 or later