www.latticesemi.com 1 TN1264_1.2

November 2015 Technical Note TN1264

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Introduction

This technical note discusses memory usage for the ECP5™ and ECP5-5G™ family of FPGA devices. It is

intended to be used by design engineers as a guide to integrating the EBR- and PFU-based memories for this

device family in Lattice Diamond

The architecture of these devices provides many resources for memory-intensive applications. The sysMEM™

Embedded Block RAM (EBR) compliments its distributed PFU-based memory. Single-Port RAM, Dual-Port RAM,

Pseudo Dual-Port RAM and ROM memories can be constructed using the EBR. The LUTs and PFUs can imple-

ment Distributed Single-Port RAM, Dual-Port RAM and ROM. Look-up Tables (LUTs) within PFUs can implement

Distributed Single-Port RAM, Dual-Port RAM and ROM.

The capabilities of the EBR Block RAM and PFU RAM are referred in this document. Designers can utilize the

memory primitives in three separate ways:

•Via Clarity Designer – The Clarity Designer GUI allows users to specify the memory type and size required. The

Clarity Designer takes this specification and constructs a netlist to implement the desired memory by using one

or more of the memory primitives.

•Via PMI (Parameterizable Module Inferencing) – PMI allows experienced users to skip the graphical interface

and utilize the Configurable memory primitives on-the-fly from the Lattice Diamond

project navigator. The

parameters and the control signals needed either in Verilog or VHDL can be set. The top-level design will have

the parameters defined and signals declared so the interface can automatically generate the black box during

synthesis.

• Via the Instantiation of Memory Primitives – Memory primitives are called directly by the top-level module and

instantiated in the user’s design. This is an advanced method and requires a thorough understanding of memory

hook-ups and design interfaces.

The remainder of this document discusses these approaches.

Memory Generation

Designers can utilize the Clarity Designer to easily specify a variety of memories in their designs. These modules

will be constructed using one or more memory primitives along with general purpose routing and LUTs as required.

The available modules in the Clarity Designer are:

• Distributed Memory Modules

– Distributed Dual Port RAM (Distributed_DPRAM)

– Distributed ROM (Distributed_ROM)

– Distributed Single Port RAM (Distributed_SPRAM)

• EBR Components (or EBR based Modules)

– Dual PORT RAM (RAM_DP_TRUE)

– Pseudo Dual Port RAM (RAM_DP)

– Single Port RAM (RAM_DQ)

– Read Only Memory (ROM)

• First In First Out Memory (FIFO and FIFO_DC)

• RAM Based Shift Register

Figure 1 shows the memory modules under Clarity Designer in Lattice Diamond software.

ECP5 and ECP5-5G

Memory Usage Guide

ECP5 and ECP5-5G Memory Usage Guide

Figure 1. Memory Modules Available in Clarity Designer

Clarity Designer Flow

Clarity Designer allows users to generate, create (or open) any of the above modules for ECP5 and ECP5-5G

devices. From the Lattice Diamond software, select Tools > Clarity Designer.

Alternatively, you can click on the button in the toolbar. This opens the Clarity Designer window as shown in

Figure 2.

Figure 2. Clarity Designer in Lattice Diamond Software

The left section of the Clarity Designer window includes the Module Tree. The Memory Modules are categorized as

Distributed RAM, EBR Components and FIFOs. The right section of the window shows the description of the

module selected and links to the documentation to find more details about it.

Let us look at an example of generating an EBR based Pseudo Dual Port RAM of size 512 x 18.