VD1D1G16XS66XX1T7B DIC DDR1 SYNCHRONOUS DYNAMIC RAM USER MANUAL
●Features:
■Stack of one 1Gbit DDR SDRAM.
■Organized as 64Mx16-bit.
■Power supply: VDD, VDDQ=2.5V±0.2V.
■Double-data-rate architecture; two data transfer per clock cycle.
■Internal pipelined operation; column address can be changed every clock cycle.
■Bidirectional data strobe.
■Differential clock inputs (CK AND #CK).
■DLL aligns DQ and DQS transition with CK transition,.
■Programmable Read Latency 2, 2.5(clock).
■Programmable Burst length (2, 4, 8).
■Programmable Burst type (sequential & interleave).
■Edge aligned data output, center aligned data input.
■Auto & Self refresh, 7.8μs refresh interval (1024/64ms refresh).
VD1D1G16XS66XX1T7B 、 D1D1G16VS66EE1T7B 、 D1D1G16VS66IB1T7B 、 VD1D1G16RS66SS1T7B 、 VD1D1G16XS66XX1T7B□ |
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User's Guide |
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Please see the document for details |
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SOP66 |
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English Chinese Chinese and English Japanese |
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Mar 23,2020 |
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Version:B0 |
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ORBITA/SIP-VD1D1G16XS66XX1T7B -USM-01 |
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291 KB |
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